A | B | C | D | E | F | G | H | CH | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
Designer | Lattice Semiconductor |
---|---|
Bits | 32-bit |
Introduced | 2006 |
Design | RISC |
Type | Register-Register |
Encoding | Fixed 32-bit |
Branching | Compare and branch |
Endianness | Big |
Extensions | User-defined |
Open | Yes, royalty free |
Registers | |
General-purpose | 32 |
LatticeMico32 is a 32-bit microprocessor reduced instruction set computer (RISC) soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs). It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.
LatticeMico32 is licensed under a free (IP) core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host architecture (FPGA, application-specific integrated circuit (ASIC), or software emulation, e.g., QEMU). It is possible to embed a LatticeMico32 core into Xilinx and Altera FPGAs, in addition to the Lattice Semiconductor parts the LatticeMico32 was developed for. AMD PowerTune uses LatticeMico32.[1]
The CPU core and the development toolchain are available as source-code, allowing third parties to implement changes to the processor architecture.
Features
- RISC load/store architecture
- 32-bit data path
- 32-bit fixed-size instructions (all instructions are 32 bits, including jump, call and branch instructions.)
- 32 general purpose registers (R0 is typically set to zero by convention, however R0 is a standard register and other values may be assigned to it if so desired.)
- Up to 32 external interrupts
- Configurable instruction set including user defined instructions
- Optional configurable caches (direct-mapped or 2-way set-associative, with a variety of cache sizes and arrangements)
- Optional pipelined memories
- Dual Wishbone memory interfaces (one read-only instruction bus, one read-write data/peripheral bus)
- Memory mapped I/O
- 6 stage pipeline
Toolchain
- GNU Compiler Collection (GCC) – C/C++ compiler; LatticeMico32 support is added in GCC 4.5.0, patches are available for support in GCC 4.4.0
- Binutils – Assembler, linker, and binary utilities; supports LatticeMico32 since version 2.19
- GNU Debugger (GDB) – Debugger
- Eclipse – Integrated development environment (IDE)
- Newlib – C library
- µCos-II, µITRON, RTEMS - real-time operating systems (RTOS)
- μClinux – operating system
See also
- Milkymist – LatticeMico32-based system on a chip (SoC)
References
- ^ "AMD x86 SMU firmware analysis". 2014-12-27.
External links
- Official website
- linux-milkymist on GitHub, uCLinux port to Milkymist SoC, that uses LatticeMico32
- jslm32 on GitHub, LatticeMico32 emulator in JavaScript, cf. Fabrice Bellard's jslinux
- ERIKA Enterprise (OSEK/VDX API) porting for LatticeMico32
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