The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Limited. These cores are optimized for low-cost and energy-efficient integrated circuits, which have been embedded in tens of billions of consumer devices.^[1] Though they are most often the main component of microcontroller chips, sometimes they are embedded inside other types of chips too. The Cortex-M family consists of Cortex-M0,^[2] Cortex-M0+,^[3] Cortex-M1,^[4] Cortex-M3,^[5] Cortex-M4,^[6] Cortex-M7,^[7] Cortex-M23,^[8] Cortex-M33,^[9] Cortex-M35P,^[10] Cortex-M52,^[11] Cortex-M55,^[12] Cortex-M85.^[13] A floating-point unit (FPU) option is available for Cortex-M4 / M7 / M33 / M35P / M52 / M55 / M85 cores, and when included in the silicon these cores are sometimes known as "Cortex-MxF", where 'x' is the core variant.

Overview

32-bit
Year	Core
2004	Cortex-M3
2007	Cortex-M1
2009	Cortex-M0
2010	Cortex-M4
2012	Cortex-M0+
2014	Cortex-M7
2016	Cortex-M23
2016	Cortex-M33
2018	Cortex-M35P
2020	Cortex-M55
2022	Cortex-M85
2023	Cortex-M52

The ARM Cortex-M family are ARM microprocessor cores that are designed for use in microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Cortex-M cores are commonly used as dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, and sensor controllers.

The main difference from Cortex-A cores is that Cortex-M cores have no memory management unit (MMU) for virtual memory, considered essential for "full-fledged" operating systems. Cortex-M programs instead run bare metal or on one of the many real-time operating systems which support a Cortex-M.

Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward. Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from 32-bit math operations, and replacing older legacy ARM cores such as ARM7 and ARM9.

License

ARM Limited neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. Arm offers a variety of licensing terms, varying in cost and deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated Device Manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions (including floating point), optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Some of the silicon options for the Cortex-M cores are:

• SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.^[14][15][16] Though the SysTick timer is optional for the M0/M0+/M1/M23, it is extremely rare to find a Cortex-M microcontroller without it. If a Cortex-M33/M35P/M52/M55/M85 microcontroller has the Security Extension option, then it optionally can have two SysTicks (one Secure, one Non-secure).
• Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region. This allows every individual bit in the bit-band region to be directly accessible from a word-aligned address. In particular, individual bits can be set, cleared, or toggled from C/C++ without performing a read-modify-write sequence of instructions.^[14][15][16] Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it. Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band.
• Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to sixteen different regions, each of which can be split further into equal-size sub-regions.^[14][15][16]
• Tightly-Coupled Memory (TCM): Low-latency (zero wait state) SRAM that can be used to hold the call stack, RTOS control structures, interrupt data structures, interrupt handler code, and speed critical code. Other than CPU cache, TCM is the fastest memory in an ARM Cortex-M microcontroller. Since TCM isn't cached and accessible at the same speed as the processor and cache, it could be conceptually described as "addressable cache". There is an ITCM (Instruction TCM) and a DTCM (Data TCM) to allow a Harvard architecture processor to read from both simultaneously. The DTCM can't contain any instructions, but the ITCM can contain data. Since TCM is tightly connected to the processor core, DMA engines might not be able to access TCM on some implementations.

ARM Cortex-M optional components

ARM Core	Cortex M0 [17]	Cortex M0+ [18]	Cortex M1 [19]	Cortex M3 [20]	Cortex M4 [21]	Cortex M7 [22]	Cortex M23 [23]	Cortex M33 [24]	Cortex M35P [10]	Cortex M52 [25]	Cortex M55 [26]	Cortex M85 [27]
SysTick 24-bit Timer	Optional (0,1)	Optional (0, 1)	Optional (0,1)	Yes (1)	Yes (1)	Yes (1)	Optional (0, 1, 2)	Yes (1, 2)	Yes (1, 2)	Yes (1, 2)	Yes (1, 2)	Yes (1, 2)
Single-cycle I/O port	No	Optional	No	No	No	No	Optional	No	No	No	No	No
Bit-Band memory	No[28]	No[28]	No*	Optional	Optional	Optional	No	No	No	No	No	No
Memory Protection Unit (MPU)	No	Optional (0, 8)	No	Optional (0,8)	Optional (0, 8)	Optional (0, 8, 16)	Optional (0, 4, 8, 12, 16)	Optional (0, 4, 8, 12, 16)	Optional (up to 16)*	Optional (0, 4, 8, 12, 16)	Optional (0, 4, 8, 12, 16)	Optional (0, 4, 8, 12, 16)
Security Attribution Unit (SAU) and Stack Limits	No	No	No	No	No	No	Optional (0, 4, 8)	Optional (0, 4, 8)	Optional (up to 8)*	Optional (0, 4, 8)	Optional (0, 4, 8)	Optional (0, 4, 8)
Instruction Cache	No[29]	No[29]	No[29]	No[29]	No[29]	Optional (up to 64 KB)	No	No	Optional (up to 16 KB)	Optional (up to 64 KB)	Optional (up to 64 KB)	Optional (up to 64 KB)
Data Cache	No[29]	No[29]	No[29]	No[29]	No[29]	Optional (up to 64 KB)	No	No	No	Optional (up to 64 KB)	Optional (up to 64 KB)	Optional (up to 64 KB)
Instruction TCM (ITCM) Memory	No	No	Optional (up to 1 MB)	No	No	Optional (up to 16 MB)	No	No	No	Optional (up to 16 MB)	Optional (up to 16 MB)	Optional (up to 16 MB)
Data TCM (DTCM) Memory	No	No	Optional (up to 1 MB)	No	No	Optional (up to 16 MB)	No	No	No	Optional (up to 16 MB)	Optional (up to 16 MB)	Optional (up to 16 MB)
ECC for TCM and Cache	No	No	No	No	No	No	No	No	Optional	Optional	Optional	Optional
Vector Table Offset Register (VTOR)	No	Optional (0,1)	Optional (0,1)	Optional (0,1)	Optional (0,1)	Optional (0,1)	Optional (0,1,2)	Yes (1,2)	Yes (1,2)	Yes (1,2)	Yes (1,2)	Yes (1,2)

• Note: Most Cortex-M3 and M4 chips have bit-band and MPU. The bit-band option can be added to the M0/M0+ using the Cortex-M System Design Kit.^[28]
• Note: Software should validate the existence of each feature before attempting to use it.^[16]
• Note: Limited public information is available for the Cortex-M35P until its Technical Reference Manual is released.

Additional silicon options:^[14][15]

• Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices.
• Interrupts: 1 to 32 (M0/M0+/M1), 1 to 240 (M3/M4/M7/M23), 1 to 480 (M33/M35P/M52/M55/M85).
• Wake-up interrupt controller: Optional.
• Vector Table Offset Register: Optional. (not available for M0).
• Instruction fetch width: 16-bit only, or mostly 32-bit.
• User/privilege support: Optional.
• Reset all registers: Optional.
• Single-cycle I/O port: Optional. (M0+/M23).
• Debug Access Port (DAP): None, SWD, JTAG and SWD. (optional for all Cortex-M cores)
• Halting debug support: Optional.
• Number of watchpoint comparators: 0 to 2 (M0/M0+/M1), 0 to 4 (M3/M4/M7/M23/M33/M35P/M52/M55/M85).
• Number of breakpoint comparators: 0 to 4 (M0/M0+/M1/M23), 0 to 8 (M3/M4/M7/M33/M35P/M52/M55/M85).

Instruction sets

The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture,^[14] the Cortex-M3 implements the ARMv7-M architecture,^[15] the Cortex-M4 / Cortex-M7 implements the ARMv7E-M architecture,^[15] the Cortex-M23 / M33 / M35P implement the ARMv8-M architecture,^[30] and the Cortex-M52 / M55 / M85 implements the ARMv8.1-M architecture.^[30] The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33 / Cortex-M35P.^[14][15] Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures; the legacy 32-bit ARM instruction set isn't supported.

All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family.

The Cortex-M0 / M0+ / M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).^[14] The Cortex-M3 / M4 / M7 / M33 / M35P have all base Thumb-1 and Thumb-2 instructions. The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit (VFPv4-SP). The Cortex-M7 adds an optional double-precision FPU (VFPv5).^[22][15] The Cortex-M23 / M33 / M35P / M52 / M55 / M85 add TrustZone instructions.

Zdroj:https://en.wikipedia.org?pojem=ARM_Cortex-M
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ARM Cortex-M instruction variations

Arm Core	Cortex M0[17]	Cortex M0+[18]	Cortex M1[19]	Cortex M3[20]	Cortex M4[21]	Cortex M7[22]	Cortex M23[23]	Cortex M33[24]	Cortex M35P	Cortex M52[25]	Cortex M55[26]	Cortex M85[27]
ARM architecture	ARMv6-M [14]	ARMv6-M [14]	ARMv6-M [14]	ARMv7-M [15]	ARMv7E-M [15]	ARMv7E-M [15]	ARMv8-M Baseline[30]	ARMv8-M Mainline[30]	ARMv8-M Mainline[30]	Armv8.1-M Mainline[30]	Armv8.1-M Mainline[30]	Armv8.1-M Mainline[30]
Computer architecture	Von Neumann	Von Neumann	Von Neumann	Harvard	Harvard	Harvard	Von Neumann	Harvard	Harvard	Harvard	Harvard	Harvard
Instruction pipeline	3 stages	2 stages	3 stages	3 stages	3 stages	6 stages	2 stages	3 stages	3 stages	4 stages	4-5 stages	7 stages
Interrupt latency (zero wait state memory)	16 cycles	15 cycles	23 for NMI, 26 for IRQ	12 cycles	12 cycles	12 cycles, 14 worst case	15 cycles, 24 secure to NS IRQ	12 cycles, 21 secure to NS IRQ	TBD	TBD	TBD	TBD
Thumb-1 instructions	Most	Most	Most	Entire	Entire	Entire	Most	Entire	Entire	Entire	Entire	Entire
Thumb-2 instructions	Some	Some	Some	Entire	Entire	Entire	Some	Entire	Entire	Entire	Entire	Entire
Multiply instructions 32×32 = 32-bit result	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Multiply instructions 32×32 = 64-bit result	No	No	No	Yes	Yes	Yes	No	Yes	Yes	Yes	Yes	Yes
Divide instructions 32/32 = 32-bit quotient	No	No	No	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Saturated math instructions	No	No	No	Some	Yes	Yes	No	Yes	Yes	Yes	Yes	Yes
DSP instructions	No	No	No	No	Yes	Yes	No	Optional	Optional	Yes	Yes	Yes