This article may need to be rewritten to comply with Wikipedia's quality standards, as it reads like a guide or textbook. You can help. The talk page may contain suggestions. (March 2021)

This article appears to be slanted towards recent events. Please try to keep recent events in historical perspective and add more content related to non-recent events. (December 2023)

Serial Peripheral Interface (SPI)

Type	Serial communication bus
Production history
Designer	Motorola
Designed	Around early 1980s[note 1]
Manufacturer	various
Daisy chain	Depends on devices
Connector	Unspecified
Electrical
Max. voltage	Unspecified
Max. current	Unspecified
Data
Width	1 bit (bidirectional)
Max. devices	Multidrop limited by chip selects. Daisy chaining unlimited.
Protocol	Full-duplex serial
Pinout
MOSI	Master Out Slave In
MISO	Master In Slave Out
SCLK	Serial Clock
CS	Chip Select (one or more)
(pins may have alternative names)

Serial Peripheral Interface (SPI) is a de facto standard (with many variants) for synchronous serial communication, used primarily in embedded systems for short-distance wired communication between integrated circuits.

SPI uses a master–slave architecture, described here with the terms "main" and "sub",^{[note 2] [1]} where one^{[note 3]} main device orchestrates communication with some number of peripheral (sub) devices by driving the clock signal and chip select signal(s).

Motorola's original specification (early 1980s) uses four wires to perform full duplex communication. It is sometimes called a four-wire serial bus to contrast with three-wire variants which are half duplex, and with the two-wire I²C and 1-Wire serial buses.

Typical applications include interfacing microcontrollers with peripheral chips for Secure Digital cards, liquid crystal displays, analog-to-digital and digital-to-analog converters, flash and EEPROM memory, and various communication chips.

SPI may be accurately described as a synchronous serial interface,^[2] but it is different from the Synchronous Serial Interface (SSI) protocol.^{[note 4]}

Operation

(Note: Variations section describes operation of non-standard variants.)

SPI has four logic signals (which may have alternative names):

Short Name	Long Name	Description (historical terms in parens)
CS	Chip Select	Active-low chip select signal from main (master) to enable communication with a specific sub (slave) device.
SCLK	Serial Clock	Clock signal from main (master) transitions for each serial data bit.
MOSI	Main Out, Sub In (master out, slave in)	Serial data from main (master), highest bit first.
MISO	Main In, Sub Out (master in, slave out)	Serial data from sub (slave), highest bit first.

MOSI on a main outputs to MOSI on a sub. MISO on a sub outputs to MISO on a main.

SPI operates with a single device acting as main and with one or more sub devices.

Sub devices should use tri-state outputs so their MISO signal becomes high impedance (electrically disconnected) when the device is not selected. Subs without tri-state outputs cannot share a MISO wire with other subs without using an external tri-state buffer.

Data transmission

To begin communication, the SPI main first selects a sub device by pulling its CS low. (Note: the bar above CS indicates it is an active low signal, so a low voltage means "selected", while a high voltage means "not selected")

If a waiting period is required, such as for an analog-to-digital conversion, the main must wait for at least that period of time before issuing clock cycles.^{[note 5]}

During each SPI clock cycle, full-duplex transmission of a single bit occurs. The main sends a bit on the MOSI line while the sub sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended.

Transmission using a single sub (Figure 1) involves one shift register in the main and one shift register in the sub, both of some given word size (e.g. 8 bits),^{[note 6]} connected in a virtual ring topology. Data is usually shifted out with the most-significant bit (MSB) first.^{[note 7]} On the clock edge, both main and sub shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the main and sub have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the main stops toggling the clock signal, and typically deselects the sub.

If a single sub device is used, its CS pin may be fixed to logic low if the sub permits it. With multiple sub devices, a multidrop configuration requires an independent CS signal from the main for each sub device, while a daisy-chain configuration only requires one CS signal.

Every sub on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent contention on MISO, non-selected subs must use tristate output. Subs that aren't already tristate will need external tristate buffers to ensure this.^[3]

Clock polarity and phase

In addition to setting the clock frequency, the main must also configure the clock polarity and phase with respect to the data. Motorola^[4][5] named these two options as CPOL and CPHA (for clock polarity and clock phase) respectively, a convention most vendors have also adopted.

The SPI timing diagram shown is further described below:

• CPOL represents the polarity of the clock. Polarities can be converted with a simple inverter.
  • SCLK_CPOL=0 is a clock which idles at the logical low voltage.
  • SCLK_CPOL=1 is a clock which idles at the logical high voltage.
• CPHA represents the phase of each data bit's transmission cycle relative to SCLK.
  • For CPHA=0:
    • The first data bit is outputted immediately when CS activates.
    • Subsequent bits are outputted when SCLK transitions to its idle voltage level.
    • Sampling occurs when SCLK transitions from its idle voltage level.
  • For CPHA=1:
    • The first data bit is outputted on SCLK's first clock edge after CS activates.
    • Subsequent bits are outputted when SCLK transitions from its idle voltage level.
    • Sampling occurs when SCLK transitions to its idle voltage level.
  • Conversion between these two phases is non-trivial.
  • Note: MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next bit's transmission cycle starts, so SPI main and sub devices may sample data at different points in that half cycle, for flexibility, despite the original specification.

Mode numbers

The combinations of polarity and phases are referred to by these "SPI mode" numbers with CPOL as the high order bit and CPHA as the low order bit:

SPI mode	Clock polarity (CPOL)	Clock phase (CPHA)	Data is shifted out on	Data is sampled on
0	0	0	falling SCLK, and when CS activates	rising SCLK
1	0	1	rising SCLK	falling SCLK
2	1	0	rising SCLK, and when CS activates	falling SCLK
3	1	1	falling SCLK	rising SCLK

Notes:

• Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1.
• In Full Duplex operation, the main device could transmit and receive with different modes. For instance, it could transmit in Mode 0 and be receiving in Mode 1 at the same time.
• Different vendors may use different naming schemes, like CKE for clock edge or NCPHA for the inversion of CPHA.

Valid communications

Some sub devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access an IC's scan chain by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).

Interrupts

Interrupts are outside the scope of SPI; their usage is neither forbidden nor specified, and so may optionally be implemented.

From main to sub

Microcontrollers configured as sub devices may have hardware support for generating interrupt signals to themselves when data words are received or overflow occurs in a receive FIFO buffer,^[6] and may also set up an interrupt routine when their chip select input line is pulled low or high.

From sub to main

SPI subs sometimes use an out-of-band signal (another wire) to send an interrupt signal to a main. Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real-time clock chips, SDIO^{[note 8]} and audio jack insertions for an audio codec. Interrupts to main may also be faked by using polling (similarly to USB 1.1 and 2.0).

Software design

SPI lends itself to a "bus driver" software design. Software for attached devices is written to call a "bus driver" that handles the actual low-level SPI hardware. This permits the driver code for attached devices to port easily to other hardware or a bit-banging software implementation.

Bit-banging the protocol

The pseudocode below outlines a software-implementation ("bit-banging") of SPI's protocol as a main with simultaneous output and input. This pseudocode is for CPHA=0 and CPOL=0, thus SCLK is pulled low before CS is activated and bits are inputted on SCLK's rising edge while bits are outputted on SCLK's falling edge.

• Initialize SCLK as low and CS as high
• Pull CS low to select the sub
• Loop for however many number of bytes to transfer:^{[note 9]}
  • Initializebyte_outwith the next output byte to transmit
  • Loop 8 times:
    • Left-Shift^{[note 10]} the next output bit frombyte_outto MOSI
    • NOP for the sub's setup time
    • Pull SCLK high
    • Left-Shift the next input bit from MISO intobyte_in
    • NOP for the sub's hold time
    • Pull SCLK low
  • byte_innow contains that recently-received byte and can be used as desired
• Pull CS high to unselect the sub

Bit-banging a sub's protocol is similar but different from above. An implementation might involve busy waiting for CS to fall or triggering an interrupt routine when CS falls, and then shifting in and out bits when the received SCLK changes appropriately for however long the transfer size is.

Bus topologies

Though the previous operation section focused on a basic interface with a single sub, SPI can instead communicate with multiple subs using multidrop, daisy chain, or expander configurations.

Multidrop configuration

In the multidrop bus configuration, each sub has its own CS, and the main selects only one at a time. MISO, SCLK, and MOSI are each shared by all devices. This is the way SPI is normally used.

Since the MISO pins of the subs are connected together, they are required to be tri-state pins (high, low or high-impedance), where the high-impedance output must be applied when the sub is not selected. Sub devices not supporting tri-state may be used in multidrop configuration by adding a tri-state buffer chip controlled by its CS signal.^[3] (Since only a single signal line needs to be tristated per sub, one typical standard logic chip that contains four tristate buffers with independent gate inputs can be used to interface up to four sub devices to an SPI bus)

Caveat: All CS signals should start high (to indicate no chips are selected) before sending initialization messages to any sub, so other uninitialized subs ignore messages not addressed to them. This is a concern if the main uses general-purpose input/output (GPIO) pins (which may default to an undefined state) for CS and if the main uses separate software libraries to initialize each device. One solution is to configure all GPIOs used for CS to output a high voltage for all subs before running initialization code from any of those software libraries. Another solution is to add a pull-up resistor on each CS, to ensure that all CS signals are initially high.^[3]

Daisy chain configuration

Some products that implement SPI may be connected in a daisy chain configuration, where the first sub's output is connected to the second sub's input, and so on with subsequent subs, until the final sub, whose output is connected back to the main's input. This effectively merges the individual communication shift registers of each sub to form a single larger combined shift register that shifts data through the chain. This configuration only requires a single CS line from the main, rather than a separate CS line for each sub.^[7]

In addition to using SPI-specific subs, daisy-chained SPI can include discrete shift registers for more pins of inputs (e.g. using the parallel-in serial-out 74xx165)^[8] or outputs (e.g. using the serial-in parallel-out 74xx595)^[9] chained indefinitely. Other applications that can potentially interoperate with daisy-chained SPI include SGPIO, JTAG,^[10] and I²C.

Expander configurations

Expander configurations use SPI-controlled addressing units (e.g. binary decoders, demultiplexers, or shift registers) to add chip selects.

For example, one CS can be used for transmitting to a SPI-controlled demultiplexer an index number controlling its select signals, while another CS is routed through that demultiplexer according to that index to select the desired sub.^[11]

Pros and cons

Advantages

• Full duplex communication in the default version of this protocol
• Push-pull drivers (as opposed to open drain) provide relatively good signal integrity and high speed
• Higher throughput than I²C or SMBus
  • SPI's protocol has no maximum clock speed, however:
    • Individual devices specify acceptable clock frequencies
    • Wiring and electronics limit frequency
• Complete protocol flexibility for the bits transferred
  • Not limited to 8-bit symbols
  • Arbitrary choice of message size, content, and purpose
• Simple hardware and interfacing
  • Hardware implementation for subs only requires a selectable shift register
    • Subs use the main's clock and hence do not need precision oscillators
    • Subs do not need a unique address – unlike I²C or GPIB or SCSI
    • Mains only additionally require generation of clock and CS signals
    • Results in simple bit-banged software implementation
  • Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than parallel interfaces
    • At most one unique signal per device (CS); all others are shared
      • Note: the daisy-chain configuration doesn't need more than one shared CS
  • Typically lower power requirements than I²C or SMBus due to less circuitry (including pull up resistors)
  • Single main means no bus arbitration (and associated failure modes) - unlike CAN-bus
  • Transceivers are not needed - unlike CAN-bus
  • Signals are unidirectional, allowing for easy galvanic isolation

Disadvantages

• Requires more pins on IC packages than I²C, even in three-wire variants
• Only handles short distances compared to RS-232, RS-485, or CAN-bus (though distance can be extended with the use of transceivers like RS-422)
• Extensibility severely reduced when multiple subs using different SPI Modes are required
  • Access is slowed down when main frequently needs to reinitialize in different modes
• No formal standard
  • So validating conformance is not possible
  • Many existing variations complicate support
• No built-in protocol support for some conveniences:
  • No hardware flow control by the sub (but the main can delay the next clock edge to slow the transfer rate)
  • No hardware sub acknowledgment (the main could be transmitting to nowhere and not know it)
  • No error-checking protocol
  • No hot swapping (dynamically adding nodes)
  • Interrupts are outside the scope of SPI (see § Interrupts)

Applications

SPI is used to talk to a variety of peripherals, such as

• Sensors: temperature, pressure, ADC, touchscreens, video game controllers
• Control devices: audio codecs, digital potentiometers, DACs
• Camera lenses: Canon EF lens mount
• Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11
• Memory: flash and EEPROMs
• Real-time clocks
• LCDs, sometimes even for managing image data
• Any MMC or SD card (including SDIO variant^{[note 8]})
• Shift registers for additional I/O^[8][9]

Board real estate and wiring savings compared to a parallel bus are significant, and have earned SPI a solid role in embedded systems. That is true for most system-on-a-chip processors, both with higher-end 32-bit processors such as those using ARM, MIPS, or PowerPC and with lower-end microcontrollers such as the AVR, PIC, and MSP430. These chips usually include SPI controllers capable of running in either main or sub mode. In-system programmable AVR controllers (including blank ones) can be programmed using SPI.^[12]

Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin. And for high-performance systems, FPGAs sometimes use SPI to interface as a sub to a host, as a main to sensors, or for flash memory used to bootstrap if they are SRAM-based.

The full-duplex capability makes SPI very simple and efficient for single main/single sub applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audio, digital signal processing, or telecommunications channels, but most off-the-shelf chips stick to half-duplex request/response protocols.

Variations

SPI is a de facto standard. However, the lack of a formal standard is reflected in a wide variety of protocol options. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some devices send the least-significant bit first. Signal levels depend entirely on the chips involved. And while the baseline SPI protocol has no command codes, every device may define its own protocol of command codes. Some variations are minor or informal, while others have an official defining document and may be considered to be separate but related protocols.

Original definition

Motorola in 1983 listed^[13] three 6805 8-bit microcomputers that have an integrated "Serial Peripheral Interface", whose functionality is described in a 1984 manual.^[14]

AN991

Motorola's 1987 Application Node AN991 "Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers"^[15] (now under NXP, last revised 2002^[5]) informally serves as the "official" defining document for SPI.

Timing variations

Some devices have timing variations from Motorola's CPOL/CPHA modes. Sending data from sub to main may use the opposite clock edge as main to sub. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response.

Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the chip select line.

Transmission size

Different transmission word sizes are common. Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits.

No chip select

Some devices don't use chip select, and instead manage protocol state machine entry/exit using other methods.

Connectorsedit

Anyone needing an external connector for SPI defines their own or uses another standard connection such as: UEXT, Pmod, various JTAG connectors, Secure Digital card socket, etc.

Flow controledit

Some devices require an additional flow control signal from sub to main, indicating when data is ready. This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the sub response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI mains do not support that signal directly, and instead rely on fixed delays.)

SafeSPIedit

SafeSPI^[16] is an industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices.

High reliability modificationsedit

In electrically noisy environments, since SPI has few signals, it can be economical to reduce the effects of common mode noise by adapting SPI to use low-voltage differential signaling.^[17] Another advantage is that the controlled devices can be designed to loop-back to test signal integrity.^[18]

Intelligent SPI controllersedit

Zdroj:https://en.wikipedia.org?pojem=Serial_Peripheral_Interface_Bus
Text je dostupný za podmienok Creative Commons Attribution/Share-Alike License 3.0 Unported; prípadne za ďalších podmienok. Podrobnejšie informácie nájdete na stránke Podmienky použitia.

---