A | B | C | D | E | F | G | H | CH | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
 National Semiconductor COP420 in 28-pin plastic DIP. Late 1982 date code. | |
| General information | |
|---|---|
| Launched | 1977 |
| Common manufacturer(s) | |
| Performance | |
| Max. CPU clock rate | to 250 KHz |
| Data width | 4 (RAM), 8 (ROM) |
| Address width | 7 (RAM), 11 (ROM) |
| Architecture and classification | |
| Application | Embedded |
| Instruction set | COP400 |
| Number of instructions | 40 |
| Physical specifications | |
| Package(s) |
|
| History | |
| Predecessor(s) | MM5799 (PMOS COP) |
| Successor(s) | COP8 |
The COP400 or COP II is a 4-bit microcontroller family introduced in 1977 by National Semiconductor as a follow-on product to their original PMOS COP microcontroller.[1] COP400 family members are complete microcomputers containing internal timing, logic, ROM, RAM, and I/O necessary to implement dedicated controllers.[2] Some COP400 devices were second-sourced by Western Digital as the WD4200 family.[3][4] In the Soviet Union several COP400 microcontrollers were manufactured as the 1820 series (e.g. the COP402 with designation КР1820ВЕ1).[5]
The COP400 is implemented in CMOS or N-channel silicon gate MOS technology. It was typically packaged in 24- or 28-pin DIP packages. Instruction cycle time of the faster family members is 4 microseconds. The COP400 family offered several memory and pinout configurations.
Notable products that used COP400-family chips include the Apple Lisa, Milton Bradley and Mattel electronic games, Coleco Head to Head Basketball, the Grundy Newbrain, and others.
Memory
The COP400 uses separate memory spaces for ROM and RAM. ROM addresses are 11-bit maximum, while data addresses are 7-bit maximum.
ROM
Program memory consists of a 512, 1024, or 2048 × 8-bit ROM. ROM bytes may be program instructions, program data, or jump address pointers. Due to the special characteristics associated with the JP and JSRP instructions, ROM must often be conceived of as organized into pages of 64 bytes each. Also, because of the unique operations performed by the LQID and JID instructions, ROM pages must sometimes be thought of as organized into blocks of 256 bytes.
RAM
Data memory consists of a 32, 64, or 128 × 4-bit RAM, organized as several data registers of 16 4-bit digits. RAM addressing is implemented by the 6- or 7-bit B register used as a pointer. The B register's upper 2 or 3 bits (Br) select one of 4 or 8 data registers and lower 4 bits (Bd) select one of 16 4-bit digits in the selected data register. The 4-bit contents of the RAM digit pointed to by the B register are usually loaded into, exchanged with, or operate on the A register.
CPU registers
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The register configuration shown in the diagram is for the COP400 family members with maximum ROM (2048 × 8 bits) and RAM (128 × 4 bits). Family members with only 512 or 1024 bytes of ROM will have only a 9- or 10-bit PC. Those with 64 or 32 locations of RAM will have only a 2-bit Br register. Some low end family members omit the SC stack register.[6]
The 4-bit A register (accumulator) is the source and destination register for most arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L port and to perform data exchanges with the SIO register.
A 4-bit ALU performs the arithmetic and logic functions, storing results in A. ASC and CASC operations output a carry to the 1-bit C register, most often employed to indicate arithmetic overflow.
All ROM addressing is accomplished via the 9-, 10-, or 11-bit PC register. Its binary value selects one of the bytes contained in ROM, usually the next program instruction. The value of PC is automatically incremented by 1 prior to the execution of the current instruction to point to the next sequential ROM location, unless the current instruction is a transfer of control instruction. In the latter case, PC is loaded with the appropriate non-sequential value to implement the transfer of control operation. The PC automatically rolls over to point to the next 64 byte page or 256 byte block of program memory. The upper 1, 2, or 3 bits of PC are also used in the JID and LQID instructions.
Three levels of subroutine are implemented by the subroutine save registers, SA, SB, and SC, providing a last-in, first-out (LIFO) hardware subroutine stack. Some implementations do not have a SC.
I/O registers and ports
There are no port numbers or memory addresses associated with the COP400 I/O devices. All the physical I/O registers and ports are referenced by the COP400 assembly language directly by name.
Baseline
Nearly all COP400 family devices implement the following:[6]
- Four general-purpose inputs, IN0-IN3, are provided. 24-pin packages do not have IN0-IN3.
- The D register provides four general purpose outputs and is the destination register for the 4-bit contents of Bd. The D register is useful for synchronizing up to 16 external devices associated with the RAM pointed to by the B register.
- The G register contains 4 general purpose bidirectional I/O ports.
- The Q register is an internal, latched, 8-bit register used to hold data loaded to or from RAM(B) and A, as well as 8-bit program data from ROM. Its contents are output to the L ports when the L drivers are enabled under program control. Also, the contents of L may be read directly into A and RAM(B).
- The SIO register functions as a 4-bit serial-in/serial-out shift register or as a binary counter depending on the contents of the EN register. Its contents can be exchanged with A, allowing it to input or output a continuous serial data stream.
- The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register.
- Though not directly accessible with software, the 10-bit time base counter divides the instruction cycle frequency by 1,024, providing a pulse upon overflow. The SKT instruction tests for the occurrence of this pulse, allowing the programmer to implement timer routines. Some low-end COP400 family members do not have this time base counter nor the SKT instruction. Some high-end COP400 devices can read and write the upper eight bits of the timer.
High end
There are a few high end members of the COP400 family such as the COP440 and COP2440 that have 40-pins. These have additional registers and ports:[7]
- The R port is an additional eight-bit bidirectional I/O port, similar to Q. The R port contains latches and drivers. Data to be output is latched into the R register. The input path is from the pins to the accumulator and RAM. Input data at the R pins are not latched into the R register by any external signal. This must be done indirectly by the program. The R drivers, like the L drivers, can be put into a high impedance state.
- These devices have an additional bidirectional four-bit port, the H port. The H port is essentially a duplicate of the G port except that H cannot be directly tested.
- The EN register is expanded to 8 bits. EN4-EN5 select interrupt sources. EN6 selects the source of the T counter. EN7 controls the output drivers of the R port. The 8-bit EN is written with the CAME instruction and read with CEMA. The lower 4 bits can be written with LEI.
Instruction set
The COP400 family is designed to have very compact code. The most frequently used instructions are one byte. In some cases there are special one-byte forms of two byte instructions. Some features that can be used to make object code more compact are:
- The LBI instruction loads the seven-bit B register with an immediate value. The general-form instruction takes two bytes. There is a one-byte form of LBI that can only set Br to 0, 1, 2, and 3 and can only set Bd to 9, 10, 11, 12, 13, 14, 15, and 0 (decimal). The single byte LBI can only access 32 RAM locations.
- Multiple LBI instructions can be stacked in series. Only the first LBI will be executed. Subsequent LBI instructions will execute as NOPs. This allows multiple entry points with different starting addresses for a shared routine.
- JSR, in the general subroutine branch form, is two bytes and can access any memory location directly. JSRP is a single byte form of subroutine branch that can access only the locations in the third 64-byte page. This page is called the subroutine page or page 2, numbered from zero. A JSRP cannot be coded from inside page 2 or 3.
- JMP, in the general branch form, is two bytes and can access any memory location directly. JP is a single byte form of branch that can access any location in the current 64-byte page. The upper bits of PC remain unchanged. If the JP instruction is executed inside page 2 or 3, then it can access any of the 128 addresses in pages 2 and 3. This is useful for creating a one byte JSRP entry point in page 2 that can then branch to a subroutine on page 3 with a single byte JP.
- The B register can be used to point to up to four RAM strings with little overhead. The LD, X, XIS, and XDS memory access instructions can Exclusive OR the lower two bits of Br with a two-bit immediate. This allows the register portion of B (Br) to be flipped to one of the other digit strings that share the same digit (Bd) address.
- The Bd register portion can be used as a memory pointer and a loop counter simultaneously. The XIS instruction will skip if Bd, after incrementing, overflows to zero, falling through the loop. Likewise the XDS instruction will skip if Bd, after decrementing, underflows to 15 (decimal).
| COP400 family instruction set | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Opcode | Operand | Mnemonic | Description | Skip | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | CLRA | A ← 0 | — |
| 0 | 0 | 0 | b0 | 0 | 0 | b1 | 1 | — | SKMBZ b | — | RAM(B)b = 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | — | XOR | A ← A ⊻ RAM(B) |
— |
| 0 | 0 | r | 0 | 1 | 0 | 0 | — | XIS r | A ↔ RAM(B), Br ← Br ⊻ r, Bd ← Bd + 1 |
Bd = 0 | |
| 0 | 0 | r | 0 | 1 | 0 | 1 | — | LD r | A ← RAM(B), Br ← Br ⊻ r |
— | |
| 0 | 0 | r | 0 | 1 | 1 | 0 | — | X r | A ↔ RAM(B), Br ← Br ⊻ r |
— | |
| 0 | 0 | r | 0 | 1 | 1 | 1 | — | XDS r | A ↔ RAM(B), Br ← Br ⊻ r, Bd ← Bd - 1 |
Bd = 15 | |
| 0 | 0 | r | 1 | d | — | LBI r,d | Br ← r, Bd ← (d + 9) ^ 15 (Br = 0-3, Bd = 9-15, 0) | next LBI | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | — | CASC | A ← ~A + RAM(B) + C, C ← Carry | carry |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | — | XABR | A ↔ Br, A3 ← 0 | — |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | — | SKC | — | C = 1 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | — | SKE | — | A = RAM(B) |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | — | SC | C ← 1 | — |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0rrrdddd | LDD r,d | A ← RAM(r,d) | — |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1rrrdddd | XAD r,d | A ↔ RAM(r,d) | — |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | — | ASC | A ← A + RAM(B) + C, C ← Carry | carry |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | — | ADD | A ← A + RAM(B) |
— |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | — | RC | C ← 0 | — |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | opcode | 33H prefix | See table below for instructions with this prefix | — |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | — | COMP | A ← ~A | — |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | — | SKT | Skip on timer overflow | timer |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | — | RMB 2 | RAM(B)2 ← 0 | — |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | — | RMB 3 | RAM(B)3 ← 0 | — |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | — | NOP | No operation | — |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | — | RMB 1 | RAM(B)1 ← 0 | — |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | — | SMB 2 | RAM(B)2 ← 1 | — |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | — | SMB 1 | RAM(B)1 ← 1 | — |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | — | RET | Pop PC (PC ← SA, SA ← SB, SB ← SC) | — |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | — | RETSK | Pop PC | always |
| 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | — | ADT | A ← A + 10 | — |
| 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | — | SMB 3 | RAM(B)3 ← 1 | — |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | — | RMB 0 | RAM(B)0 ← 0 | — |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | — | SMB 0 | RAM(B)0 ← 1 | — |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | — | CBA | A ← Bd | — |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | — | XAS | A ↔ SIO, SK ← C | — |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | — | CAB | Bd ← A | — |
| 0 | 1 | 0 | 1 | y | — | AISC y | A ← A + y (1 ≤ y ≤ 15) | carry | |||
| 0 | 1 | 1 | 0 | 0 | addhi | addlo | JMP a | PC ← addhi, PC ← addlo | — | ||
| 0 | 1 | 1 | 0 | 1 | addhi | addlo | JSR a | Push PC, PC ← addhi, PC ← addlo | — | ||
| 0 | 1 | 1 | 1 | y | — | STII y | RAM(B) ← y, Bd ← Bd + 1 | — | |||
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