A | B | C | D | E | F | G | H | CH | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
| PCI Local Bus | |
 Three 5-volt 32-bit PCI expansion slots on a motherboard (PC bracket on left side) | |
| Year created | June 22, 1992[1] |
|---|---|
| Created by | Intel |
| Supersedes | ISA, EISA, MCA, VLB |
| Superseded by | AGP for graphics (1997), PCI Express (2004) |
| Width in bits | 32 or 64 |
| Speed | Half-duplex:[2]
133 MB/s (32-bit at 33 MHz – the standard configuration) 266 MB/s (32-bit at 66 MHz) 266 MB/s (64-bit at 33 MHz) 533 MB/s (64-bit at 66 MHz) |
| Style | Parallel |
| Hotplugging interface | Optional |
| Website | www |
Peripheral Component Interconnect (PCI)[3] is a local computer bus for attaching hardware devices in a computer and is part of the PCI Local Bus standard. The PCI bus supports the functions found on a processor bus but in a standardized format that is independent of any given processor's native bus. Devices connected to the PCI bus appear to a bus master to be connected directly to its own bus and are assigned addresses in the processor's address space.[4] It is a parallel bus, synchronous to a single bus clock. Attached devices can take either the form of an integrated circuit fitted onto the motherboard (called a planar device in the PCI specification) or an expansion card that fits into a slot. The PCI Local Bus was first implemented in IBM PC compatibles, where it displaced the combination of several slow Industry Standard Architecture (ISA) slots and one fast VESA Local Bus (VLB) slot as the bus configuration. It has subsequently been adopted for other computer types. Typical PCI cards used in PCs include: network cards, sound cards, modems, extra ports such as Universal Serial Bus (USB) or serial, TV tuner cards and hard disk drive host adapters. PCI video cards replaced ISA and VLB cards until rising bandwidth needs outgrew the abilities of PCI. The preferred interface for video cards then became Accelerated Graphics Port (AGP), a superset of PCI, before giving way to PCI Express.[5]
The first version of PCI found in retail desktop computers was a 32-bit bus using a 33 MHz bus clock and 5 V signaling, although the PCI 1.0 standard provided for a 64-bit variant as well.[clarification needed] These have one locating notch in the card. Version 2.0 of the PCI standard introduced 3.3 V slots, physically distinguished by a flipped physical connector to prevent accidental insertion of 5 V cards. Universal cards, which can operate on either voltage, have two notches. Version 2.1 of the PCI standard introduced optional 66 MHz operation. A server-oriented variant of PCI, PCI Extended (PCI-X) operated at frequencies up to 133 MHz for PCI-X 1.0 and up to 533 MHz for PCI-X 2.0. An internal connector for laptop cards, called Mini PCI, was introduced in version 2.2 of the PCI specification. The PCI bus was also adopted for an external laptop connector standard – the CardBus.[6] The first PCI specification was developed by Intel, but subsequent development of the standard became the responsibility of the PCI Special Interest Group (PCI-SIG).[7]
PCI and PCI-X sometimes are referred to as either Parallel PCI or Conventional PCI[8] to distinguish them technologically from their more recent successor PCI Express, which adopted a serial, lane-based architecture.[9][10] PCI's heyday in the desktop computer market was approximately 1995 to 2005.[9] PCI and PCI-X have become obsolete for most purposes and has largely disappeared from many other modern motherboards since 2013; however they are still common on some modern desktops as of 2020[update] for the purposes of backward compatibility and the relative low cost to produce. Another common modern application of parallel PCI is in industrial PCs, where many specialized expansion cards, used here, never transitioned to PCI Express, just as with some ISA cards. Many kinds of devices formerly available on PCI expansion cards are now commonly integrated onto motherboards or available in USB and PCI Express versions.
History
Work on PCI began at the Intel Architecture Labs (IAL, also Architecture Development Lab) c. 1990. A team of primarily IAL engineers defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations.
PCI was immediately put to use in servers, replacing Micro Channel architecture (MCA) and Extended Industry Standard Architecture (EISA) as the server expansion bus of choice. In mainstream PCs, PCI was slower to replace VLB, and did not gain significant market penetration until late 1994 in second-generation Pentium PCs. By 1996, VLB was all but extinct, and manufacturers had adopted PCI even for Intel 80486 (486) computers.[11] EISA continued to be used alongside PCI through 2000. Apple Computer adopted PCI for professional Power Macintosh computers (replacing NuBus) in mid-1995, and the consumer Performa product line (replacing LC Processor Direct Slot (PDS)) in mid-1996.
Outside the server market, the 64-bit version of plain PCI remained rare in practice though,[12] although it was used for example by all (post-iMac) G3 and G4 Power Macintosh computers.[13]
Later revisions of PCI added new features and performance improvements, including a 66 MHz 3.3 V standard and 133 MHz PCI-X, and the adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards. These revisions were used on server hardware but consumer PC hardware remained nearly all 32-bit, 33 MHz and 5 volt.
The PCI-SIG introduced the serial PCI Express in c. 2004. Since then, motherboard manufacturers have included progressively fewer PCI slots in favor of the new standard. Many new motherboards do not provide PCI slots at all, as of late 2013. [citation needed]
| Spec | Year | Change summary[15] |
|---|---|---|
| PCI 1.0 | 1992 | Original issue |
| PCI 2.0 | 1993 | Incorporated connector and add-in card specification |
| PCI 2.1 | 1995 | Incorporated clarifications and added 66 MHz chapter |
| PCI 2.2 | 1998 | Incorporated ECNs, and improved readability |
| PCI 2.3 | 2002 | Incorporated ECNs, errata, and deleted 5 volt only keyed add-in cards |
| PCI 3.0 | 2004 | Removed support for 5.0 volt keyed system board connector |
Auto configuration
PCI provides separate memory and memory-mapped I/O port address spaces for the x86 processor family, 64 and 32 bits, respectively. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or input/output (I/O) port space via its configuration space registers.
In a typical system, the firmware (or operating system) queries all PCI buses at startup time (via PCI Configuration Space) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is.
The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.
Devices may have an on-board read-only memory (ROM) containing executable code for x86 or PA-RISC processors, an Open Firmware driver, or an Option ROM. These are typically needed for devices used during system startup, before device drivers are loaded by the operating system.
In addition, there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly. "Fair" in this case means that devices will not use such a large portion of the available PCI bus bandwidth that other devices are not able to get needed work done. Note, this does not apply to PCI Express.
How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data.[16]
Interrupts
Devices are required to follow a protocol so that the interrupt-request (IRQ) lines can be shared. The PCI bus includes four interrupt lines, INTA# through INTD#, all of which are available to each device. Up to eight PCI devices share the same IRQ line (LNKA through LNKH) in APIC-enabled x86 systems. Interrupt lines are not wired in parallel as are the other PCI bus lines. The positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that. Single-function devices usually use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts.
The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent. Platform-specific firmware or operating system code is meant to know this, and set the "interrupt line" field in each device's configuration space indicating which IRQ it is connected to.
PCI interrupt lines are level-triggered. This was chosen over edge-triggering to gain an advantage when servicing a shared interrupt line, and for robustness: edge-triggered interrupts are easy to miss.
Later revisions of the PCI specification add support for message-signaled interrupts. In this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message signaling is in-band, it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines.
PCI Express does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively.
Conventional hardware specifications
These specifications represent the most common version of PCI used in normal PCs:
- 33.33 MHz clock with synchronous transfers
- Peak transfer rate of 133 MB/s (133 megabytes per second) for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)
- 32-bit bus width
- 32- or 64-bit memory address space (4 GiB or 16 EiB)
- 32-bit I/O port space
- 256-byte (per device) configuration space
- 5-volt signaling
- Reflected-wave switching
The PCI specification also provides options for 3.3 V signaling, 64-bit bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.
The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master.
Card voltage and keying
Typical PCI cards have either one or two key notches, depending on their signaling voltage. Cards requiring 3.3 volts have a notch 56.21 mm from the card backplate; those requiring 5 volts have a notch 104.41 mm from the backplate. This allows cards to be fitted only into slots with a voltage they support. "Universal cards" accepting either voltage have both key notches.
Connector pinout
The PCI connector is defined as having 62 contacts on each side of the edge connector, but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side. Side A refers to the 'solder side' and side B refers to the 'component side': if the card is held with the connector pointing down, a view of side A will have the backplate on the right, whereas a view of side B will have the backplate on the left. The pinout of B and A sides are as follows, looking down into the motherboard connector (pins A1 and B1 are closest to backplate).[15][17][18]
| Pin | Side B | Side A | Comments | ||
|---|---|---|---|---|---|
| 1 | −12 V | TRST# | JTAG port pins (optional) | ||
| 2 | TCK | +12 V | |||
| 3 | Ground | TMS | |||
| 4 | TDO | TDI | |||
| 5 | +5 V | +5 V | |||
| 6 | +5 V | INTA# | Interrupt pins (open-drain) | ||
| 7 | INTB# | INTC# | |||
| 8 | INTD# | +5 V | |||
| 9 | PRSNT1# | Reserved | Pulled low to indicate 7.5 or 25 W power required | ||
| 10 | Reserved | IOPWR | +5 V or +3.3 V | ||
| 11 | PRSNT2# | Reserved | Pulled low to indicate 7.5 or 15 W power required | ||
| 12 | Ground | Ground | Key notch for 3.3 V-capable cards | ||
| 13 | Ground | Ground | |||
| 14 | Reserved | 3.3 V aux | Standby power (optional) | ||
| 15 | Ground | RST# | Bus reset | ||
| 16 | CLK | IOPWR | 33/66 MHz clock | ||
| 17 | Ground | GNT# | Bus grant from motherboard to card | ||
| 18 | REQ# | Ground | Bus request from card to motherboard | ||
| 19 | IOPWR | PME# | Power management event (optional) 3.3 V, open drain, active low.[19] | ||
| 20 | AD | AD | Address/data bus (upper half) | ||
| 21 | AD | +3.3 V | |||
| 22 | Ground | AD | |||
| 23 | AD | AD | |||
| 24 | AD | Ground | |||
| 25 | +3.3 V | AD | |||
| 26 | C/BE# | IDSEL | |||
| 27 | AD | +3.3 V | |||
| 28 | Ground | AD | |||
| 29 | AD | AD | |||