This article relies excessively on references to primary sources. Please improve this article by adding secondary or tertiary sources. Find sources: "International Symposium on Microarchitecture" – news · newspapers · books · scholar · JSTOR (September 2011) (Learn how and when to remove this message)

MICRO, IEEE/ACM International Symposium on Microarchitecture
Status	Active
Genre	Computer Architecture Conference
Inaugurated	1968 (Bedford, Massachusetts)
Most recent	2023 (Toronto, Ontario)
Organized by	ACM SIGMICRO and IEEE Computer Society
Website	microarch.org

The IEEE/ACM International Symposium on Microarchitecture^® (MICRO) is an annual academic conference on microarchitecture, generally viewed as the top-tier academic conference on computer architecture.^[1] It is not to be confused with a micro-conference. Particularly within the domains of microarchitecture and Code generation (compiler), MICRO is unrivaled and esteemed as the premier forum. Association for Computing Machinery's Special Interest Group on Microarchitecture (ACM SIGMICRO) and Institute of Electrical and Electronics Engineers Computer Society are technical sponsors.

MICRO Test of Time (ToT) Award

The ToT award will recognize an influential MICRO paper whose influence is still felt 18–22 years after its initial publication. Most of ToT awarded papers have received around 1000 citations (according to Google Scholar).

Prior recipients include:

• 2022 (For MICRO 2003) A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
• 2022 (For MICRO 2003) Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
• 2021 (For MICRO 2003) Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
• 2021 (For MICRO 2003) Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
• 2020 (For MICRO 1998) A Dynamic Multithreading Processor
• 2019 (For MICRO 2001) Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution
• 2018 (For MICRO 1996) Assigning Confidence to Conditional Branch Predictions
• 2018 (For MICRO 1996) Efficient Path Profiling
• 2017 (For MICRO 1996) Exceeding the Dataflow Limit Via Value Prediction
• 2016 (For MICRO 1994) Iterative modulo scheduling: an algorithm for software pipelining loops
• 2015 (For MICRO 1996) Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
• 2015 (For MICRO 1992) Effective Compiler Support For Predicated Execution Using the Hyperblock
• 2014 (For MICRO 1991) Two-Level Branch Predictor
• 2014 (For MICRO 1982) MIPS: A Microprocessor Architecture
• 2014 (For MICRO 1981) Some Scheduling Techniques and An Easily Schedulable Horizontal Architecture for High Performance Scientific Computing
• 2014 (For MICRO 1978) Microprogrammed Implementation of A Single Chip Microprocessor

References