MCS-80 - Biblioteka.sk

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MCS-80
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Intel 8080
Closed and open Intel 8080 processor
General information
LaunchedApril 1974; 49 years ago (1974-04)
Discontinued1990; 34 years ago (1990)[1]
Marketed byIntel
Designed byIntel
Common manufacturer(s)
  • Intel
Performance
Max. CPU clock rate2 MHz to 3.125 MHz
Data width8 bits
Address width16 bits
Architecture and classification
Technology node6 µm
Instruction set8080
Physical specifications
Transistors
  • 4,500 or 6,000[2]
Cores
  • 1
Package(s)
Socket(s)
History
Predecessor(s)Intel 8008
Successor(s)Intel 8085
Support status
Unsupported

The Intel 8080 ("eighty-eighty") is the second 8-bit microprocessor designed and manufactured by Intel. It first appeared in April 1974 and is an extended and enhanced variant of the earlier 8008 design, although without binary compatibility.[3] The initial specified clock rate or frequency limit was 2 MHz, with common instructions using 4, 5, 7, 10, or 11 cycles. As a result, the processor is able to execute several hundred thousand instructions per second. Two faster variants, the 8080A-1 and 8080A-2, became available later with clock frequency limits of 3.125 MHz and 2.63 MHz respectively.[4] The 8080 needs two support chips to function in most applications: the i8224 clock generator/driver and the i8228 bus controller. It is implemented in N-type metal–oxide–semiconductor logic (NMOS) using non-saturated enhancement mode transistors as loads[5][6] thus demanding a +12 V and a −5 V voltage in addition to the main transistor–transistor logic (TTL) compatible +5 V.

Although earlier microprocessors were commonly used in mass-produced devices such as calculators, cash registers, computer terminals, industrial robots,[7] and other applications, the 8080 saw greater success in a wider set of applications, and is largely credited with starting the microcomputer industry.[8] Several factors contributed to its popularity: its 40-pin package made it easier to interface than the 18-pin 8008, and also made its data bus more efficient; its NMOS implementation gave it faster transistors than those of the P-type metal–oxide–semiconductor logic (PMOS) 8008, while also simplifying interfacing by making it TTL-compatible; a wider variety of support chips were available; its instruction set was enhanced over the 8008;[9] and its full 16-bit address bus (versus the 14-bit one of the 8008) enabled it to access 64 KB of memory, four times more than the 8008's range of 16 KB. It was used in the Altair 8800 and subsequent S-100 bus personal computers until it was replaced by the Z80 in this role, and was the original target CPU for CP/M operating systems developed by Gary Kildall.

The 8080 directly influenced the later x86 architecture. Intel designed the 8086 to have its assembly language be similar enough to the 8080, with most instructions mapping directly onto each other, that transpiled 8080 assembly code could be executed on the 8086.[10]

History

Microprocessor customers were reluctant to adopt the 8008 because of limitations such as the single addressing mode, low clock speed, low pin count, and small on-chip stack, which restricted the scale and complexity of software. There were several proposed designs for the 8080, ranging from simply adding stack instructions to the 8008 to a complete departure from all previous Intel architectures.[11] The final design was a compromise between the proposals.

Federico Faggin, the originator of the 8080 architecture in early 1972, proposed the chip to Intel's management and pushed for its implementation. He finally got the permission to develop it six months later. Faggin hired Masatoshi Shima, who helped design the 4004 with him, from Japan in November 1972. Shima did the detailed design under Faggin's direction,[12] using the design methodology for random logic with silicon gate that Faggin had created for the 4000 family.

The 8080 was explicitly designed to be a general-purpose microprocessor for a larger number of customers. Much of the development effort was spent trying to integrate the functionalities of the 8008's supplemental chips into one package. It was decided early in development that the 8080 was not to be binary-compatible with the 8008, instead opting for source compatibility once run through a transpiler, to allow new software to not be subject to the same restrictions as the 8008. For the same reason, as well as to expand the capabilities of stack-based routines and interrupts, the stack was moved to external memory.

Noting the specialized use of general-purpose registers by programmers in mainframe systems, Stanley Mazor, the chip architect, decided the 8080's registers would be specialized, with register pairs having a different set of uses.[13] This also allowed the engineers to more effectively use transistors for other purposes.

Shima finished the layout in August 1973. After the regulation of NMOS fabrication, a prototype of the 8080 was completed in January 1974. It had a flaw, in that driving with standard TTL devices increased the ground voltage because high current flowed into the narrow line. Intel had already produced 40,000 units of the 8080 at the direction of the sales section before Shima characterized the prototype. It was released as requiring Low-power Schottky TTL (LS TTL) devices. The 8080A fixed this flaw.[14]

Intel offered an instruction set simulator for the 8080 named INTERP/80 to run compiled PL/M programs. It was written in FORTRAN IV by Gary Kildall while he worked as a consultant for Intel.[15][16]

Description

Programming model

i8080 microarchitecture
Intel 8080 registers
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
Main registers
A Flags Program Status Word
B C B
D E D
H L H (indirect address)
Index registers
SP Stack Pointer
Program counter
PC Program Counter
Status register
  S Z 0 AC 0 P 1 C Flags [17]

The Intel 8080 is the successor to the 8008. It uses the same basic instruction set and register model as the 8008, although it is neither source code compatible nor binary code compatible with its predecessor. Every instruction in the 8008 has an equivalent instruction in the 8080. The 8080 also adds 16-bit operations in its instruction set. Whereas the 8008 required the use of the HL register pair to indirectly access its 14-bit memory space, the 8080 added addressing modes to allow direct access to its full 16-bit memory space. The internal 7-level push-down call stack of the 8008 was replaced by a dedicated 16-bit stack-pointer (SP) register. The 8080's 40-pin DIP packaging permits it to provide a 16-bit address bus and an 8-bit data bus, enabling access to 64 KiB (216 bytes) of memory.

Registers

The processor has seven 8-bit registers (A, B, C, D, E, H, and L), where A is the primary 8-bit accumulator. The other six registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE, and HL, referred to as B, D and H in Intel documents) depending on the particular instruction. Some instructions also enable the HL register pair to be used as a (limited) 16-bit accumulator. A pseudo-register M, which refers to the dereferenced memory location pointed to by HL, can be used almost anywhere other registers can be used. The 8080 has a 16-bit stack pointer to memory, replacing the 8008's internal stack, and a 16-bit program counter.

Flags

The processor maintains internal flag bits (a status register), which indicate the results of arithmetic and logical instructions. Only certain instructions affect the flags. The flags are:

  • Sign (S), set if the result is negative.
  • Zero (Z), set if the result is zero.
  • Parity (P), set if the number of 1 bits in the result is even.
  • Carry (C), set if the last addition operation resulted in a carry or if the last subtraction operation required a borrow
  • Auxiliary carry (AC or H), used for binary-coded decimal arithmetic (BCD).

The carry bit can be set or complemented by specific instructions. Conditional-branch instructions test the various flag status bits. The accumulator and the flags together are called the PSW, or program status word. PSW can be pushed to or popped from the stack.

Commands, instructions

As with many other 8-bit processors, all instructions are encoded in one byte (including register numbers, but excluding immediate data), for simplicity. Some can be followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. Like more advanced processors, it has automatic CALL and RET instructions for multi-level procedure calls and returns (which can even be conditionally executed, like jumps) and instructions to save and restore any 16-bit register pair on the machine stack. Eight one-byte call instructions (RST) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke a corresponding interrupt service routine, but are also often employed as fast system calls. The instruction that executes slowest is XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.

8-bit instructions

All 8-bit operations with two operands can only be performed on the 8-bit accumulator (the A register). The other operand can be either an immediate value, another 8-bit register, or a memory byte addressed by the 16-bit register pair HL. Increments and decrements can be performed on any 8 bit register or an HL-addressed memory byte. Direct copying is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory byte. Due to the regular encoding of the MOV instruction (using a quarter of available opcode space), there are redundant codes to copy a register into itself (MOV B,B, for instance), which are of little use, except for delays. However, the systematic opcode for MOV M,M is instead used to encode the halt (HLT) instruction, halting execution until an external reset or interrupt occurs.

16-bit operations

Although the 8080 is generally an 8-bit processor, it has limited abilities to perform 16-bit operations. Any of the three 16-bit register pairs (BC, DE, or HL, referred to as B, D, H in Intel documents) or SP can be loaded with an immediate 16-bit value (using LXI), incremented or decremented (using INX and DCX), or added to HL (using DAD). By adding HL to itself, it is possible to achieve the same result as a 16-bit arithmetical left shift with one instruction. The only 16-bit instructions that affect any flag is DAD, which sets the CY (carry) flag in order to allow for programmed 24-bit or 32-bit arithmetic (or larger), needed to implement floating-point arithmetic. A stack frame can be allocated using DAD SP and SPHL. A branch to a computed pointer can be executed with PCHL. LHLD loads HL from directly addressed memory and SHLD stores HL likewise. The XCHG[18] instruction exchanges the values of the HL and DE register pairs. XTHLexchanges last item pushed on stack with HL.

Instruction set
Zdroj:https://en.wikipedia.org?pojem=MCS-80
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Opcode Operands Mnemonic Cycles Description
7 6 5 4 3 2 1 0 b2 b3
0 0 0 0 0 0 0 0 NOP 4 No operation
0 0 RP 0 0 0 1 datlo dathi LXI rp,data 10 RP ← data
0 0 RP 0 0 1 0 STAX rp 7 (RP) ← A
0 0 RP 0 0 1 1 INX rp 5 RP ← RP + 1
0 0 DDD 1 0 0 INR ddd 5/10 DDD ← DDD + 1
0 0 DDD 1 0 1 DCR ddd 5/10 DDD ← DDD - 1
0 0 DDD 1 1 0 data MVI ddd,data 7/10 DDD ← data
0 0 RP 1 0 0 1 DAD rp 10 HL ← HL + RP
0 0 RP 1 0 1 0 LDAX rp 7 A ← (RP)
0 0 RP 1 0 1 1 DCX rp 5 RP ← RP - 1
0 0 0 0 0 1 1 1 RLC 4 A1-7 ← A0-6; A0 ← Cy ← A7
0 0 0 0 1 1 1 1 RRC 4 A0-6 ← A1-7; A7 ← Cy ← A0
0 0 0 1 0 1 1 1 RAL 4 A1-7 ← A0-6; Cy ← A7; A0 ← Cy
0 0 0 1 1 1 1 1 RAR 4 A0-6 ← A1-7; Cy ← A0; A7 ← Cy
0 0 1 0 0 0 1 0 addlo addhi SHLD add 16 (add) ← HL
0 0 1 0 0 1 1 1 DAA 4 If A0-3 > 9 OR AC = 1 then A ← A + 6;

then if A4-7 > 9 OR Cy = 1 then A ← A + 0x60

0 0 1 0 1 0 1 0 addlo addhi LHLD add 16 HL ← (add)
0 0 1 0 1 1 1 1 CMA 4 A ← ¬A
0 0 1 1 0 0 1 0 addlo addhi STA add 13 (add) ← A
0 0 1 1 0 1 1 1 STC 4 Cy ← 1
0 0 1 1 1 0 1 0 addlo addhi LDA add 13 A ← (add)
0 0 1 1 1 1 1 1 CMC 4 Cy ← ¬Cy
0 1 DDD SSS MOV ddd,sss 5/7 DDD ← SSS
0 1 1 1 0 1 1 0 HLT 7 Halt
1 0 ALU SSS ADD ADC SUB SBB ANA XRA ORA CMP sss 4/7 A ← A SSS
1 1 CC 0 0 0 Rcc 5/11 If cc true, PC ← (SP), SP ← SP + 2
1 1 RP 0 0 0 1 POP rp 10 RP ← (SP), SP ← SP + 2
1 1 CC 0 1 0 addlo addhi Jcc add 10 If cc true, PC ← add
1 1 0 0 0 0 1 1 addlo addhi JMP add 10 PC ← add
1 1 CC 1 0 0 addlo addhi Ccc add 11/17 If cc true, SP ← SP - 2, (SP) ← PC, PC ← add
1 1 RP 0 1 0 1 PUSH rp 11 SP ← SP - 2, (SP) ← RP
1 1 ALU 1 1 0 data